| Course description: | 2 hours lecture, 2 hours laboratory. This course introduces students to digital design systems using very high speed integrated circuit hardware description languages (VHDL). The course provides design approaches which partition a system into a data-path and controller and focuses on synthesizable VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. The course introduces VHDL simulation and verification, and FPGA and CPLD synthesis, placement, routing, timing analysis and performance optimization. The material covered in the lecture is reinforced through hands-on experience in the associated lab. Prerequisites: EET 340. Concurrent enrollment: EET 343L. (F) |
|---|